View HI56308CN_1014212.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
T DUC EN T P R O LA C E M r a t E TE R E P e nt e OL OBS ENDED upport C om/tsc M S il.c ical COM nters Data ur Te n March 2003 O RE Sheetch r www.i N o to ntac TERSIL co 8-IN 1-88
HI5630
FN4645.3
Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference
The HI5630 is a monolithic, triple 8-bit, 80MSPS analog-to-digital converter fabricated in an advanced CMOS process. It is designed for digitizing RGB graphics from work stations and personal computers. The HI5630 reaches a new level of multi-channel integration. The fully pipeline architecture and an innovative input stage enable the HI5630 to accept a variety of single-ended or fully differential input configurations which present valid data to the output bus with a latency of 5 clock cycles. Only one external clock is necessary to drive all three converters with a clock out signal provided. An internal band-gap voltage reference is also provided allowing the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. The HI5630 can be bench tested using a complete ADC evaluation board with clock drivers, ADC, latches and a reconstruct DAC. In addition, complete LCD monitor reference designs are available for immediate volume production (contact factory).
Features
* Triple 8-Bit A/D Converter on a Monolithic Chip * Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 80MSPS * ENOB (fIN = 1MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 * Wide Full Power Input Bandwidth . . . . . . . . . . . . 300MHz * Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V * Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB * Single Supply Voltage Operation . . . . . . . . . . . . . . . . .+5V * On-Chip Sample and Hold Amplifiers * Clock Output * Offset Binary or Two's Complement Output Format * Stand-By Low Power mode
Applications
* LCD Monitors, Projectors and Plasma Display Panels * Video Digitizing (RGB, Composite or Y-C) * Medical Imaging
Part Number Information
TEMP. PART NUMBER RANGE (oC) HI5630/8CN HI5630EVAL1 0 to 70 25 PACKAGE 64 Ld MQFP PKG. NO. Q64.14x14
* High Speed Multi-Channel Data Acquisition
Pinout
HI5630 (MQFP) TOP VIEW
BD6 BD5 BD4 BD3 DGND DVDD BD2 BD1 BD0 N/C DFS STBY AGND AVDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 N/C GD7 RD0 RD1 RD2 RD3 RD4 DGND DVDD RD5 RD6 RD7 N/C AGND AVDD AGND AGND BIN + BIN BVDC AGND VRIN VROUT AVDD GIN + GIN GVDC AGND AVDD RIN + RIN RVDC GD0 BD7 DGND DVDD GD1 GD2 GD3 DGND DVDD CLKOUT CLKIN DVDD DGND GD4 GD5 GD6 DVDD DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ADC Evaluation Platform
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HI5630 Functional Block Diagram
RVDC RINRIN+ S/H DC BIAS
STAGE M - 6 RD0 (LSB) RD1 RD2 2-BIT FLASH 2-BIT DAC RD3 RD4 RD5 RD6 + X2 GD0 (LSB) GD1 GD2 GD3 X2 STAGE M GD4 GD5 GD6 GD7 (MSB) 2-BIT FLASH DIGITAL DELAY AND DIGITAL ERROR CORRECTION RD7 (MSB)
-
BD0 (LSB) BD1 BD2 BD3
GVDC GINGIN+
SAME AS RED ABOVE
BD4 BD5 BD6 BD7 (MSB)
BVDC BINB N+
SAME AS RED ABOVE
DFS STBY CLKIN CLKOUT
VROUT VRIN REFERENCE POWER
AVDD
AGND
DVDD
DGND
2
HI5630 Typical Video Application Schematic
AVDD DVDD
HI5630
RIN +
(35) RIN + (33) RVDC (2V) 0.1F (34) RIN -
(LSB) RD0 (19) RD1 (20) RD2 (21) RD3 (22) RD4 (23) RD5 (26) RD6 (27) (MSB) RD7 (28)
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
GIN +
(40) GIN + (38) GVDC (2V) 0.1F (39) GIN -
DGND BIN + (47) BIN + (45) BVDC (2V) 0.1F (46) BIN (LSB) GD0 (64) GD1 (3) GD2 (4) GD3 (5) GD4 (12) GD5 (13) GD6 (14) (MSB) GD7 (18) GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7
DGND (LSB) BD0 (54) BD1 (55) (43) VRIN (42) VROUT 1.0F BD2 (56) BD3 (59) BD4 (60) BD5 (61) BD6 (62) DGND DVDD (51) STBY (52) DFS (MSB) BD7 (63) DGND BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7
CLOCK IN
(9) CLK IN AGND
CLK OUT (8) DGND
CLOCK OUT
AGND
DGND
3
HI5630 Pin Description
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME DGND DVDD GD1 GD2 GD3 DGND DVDD CLK OUT CLK IN DVDD DGND GD4 GD5 GD6 DVDD DGND NC GD7 RD0 RD1 RD2 RD3 RD4 DGND DVDD RD5 RD6 RD7 NC AGND AVDD AGND DESCRIPTION Digital Ground Digital Supply (5.0V) Green Data Bit 1 Output Green Data Bit 2 Output Green Data Bit 3 Output Digital Ground Digital Supply (5.0V) Sample Clock Output Sample Clock Input Digital Supply (5.0V) Digital Ground Green Data Bit 4 Output Green Data Bit 5 Output Green Data Bit 6 Output Digital Supply (5.0V) Digital Ground No Connection Green Data Bit 7 Output Red Data Bit 0 Output Red Data Bit 1 Output Red Data Bit 2 Output Red Data Bit 3 Output Red Data Bit 4 Output Digital Ground Digital Supply (5.0V) Red Data Bit 5 Output Red Data Bit 6 Output Red Data Bit 7 Output No Connection Analog Ground Analog Supply (5.0V) Analog Ground
Pin Description
PIN NO. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME RVDC RINRIN+ AVDD AGND GVDC GINGIN+ AVDD VROUT VRIN AGND BVDC BINBIN+ AGND AVDD AGND STBY DFS NC BD0 BD1 BD2 DVDD DGND BD3 BD4 BD5 BD6 BD7 GD0
(Continued) DESCRIPTION Red DC Bias Voltage Output (2.0) Red Negative Analog Input Red Positive Analog Input Analog Supply (5.0V) Analog Ground Green DC Bias Voltage Output Green Negative Analog Input Green Positive Analog Input Analog Supply (5.0V) +2.5V Reference Voltage Output +2.5V Reference Voltage Input Analog Ground Blue DC Bias Voltage Output Blue Negative Analog Input Blue Positive Analog Input Analog Ground Analog Supply (5.0V) Analog Ground Stand-By Power Mode Data Format Select Input No Connection Blue Data Bit 0 Output Blue Data Bit 1 Output Blue Data Bit 2 Output Digital Supply (5.0V) Digital Ground Blue Data Bit 3 Output Blue Data Bit 4 Output Blue Data Bit 5 Output Blue Data Bit 6 Output Blue Data Bit 7 Output Green Data Bit 0 Output
4
HI5630
Absolute Maximum Ratings TA = 25oC
Supply Voltage, AVDD or DVDD to AGND or DGND . . . . . . . . . . .6V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVDD Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVDD
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
Operating Conditions
Temperature Range HI5630/8CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
MQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a 1S2P (1 Signal and 2 Power) evaluation PC board in free air.
Electrical Specifications
PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Channel Offset Match Channel Full Scale Error Match Offset Code, VOC Full Scale Error, FSE Bit Error Rate (BER) ANALOG INPUT Analog Input Range Analog Input Resistance Analog Input Capacitance Analog Input Bias Current
AVDD = 5V, DVDD = 5V; Single Ended Inputs, VRIN = 2.5V; fS = 80MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
fIN = 1MHz fIN = 1MHz fIN = DC fIN = DC VIN+ = VINfIN = DC -
8 0.4 0.2 1 0.25 140 1 -
2.0 1.0 -
Bits LSB LSB LSB LSB CODE LSB s
(Note 2) VIN+ = VIN- = VREF VIN+ = VIN- = VREF
-10 -
0.95 1 10 1.0 300
1 10 -
V M pF A MHz
Full Power Input Bandwidth, FPBW INTERNAL VOLTAGE REFERENCE 1F Decoupling Cap Needed Reference Output Voltage, VREF Reference Output Current, IROUT Reference Temperature Coefficient DC BIAS PINS RVDC, GVDC, BVDC with 0.1F Decoupling Cap Needed VDC Output Voltage (Loaded) VDC Output Current, IVDC VDC Temperature Coefficient REFERENCE VOLTAGE INPUT Reference Voltage Input, VRIN Total Reference Resistance, RRIN Reference Current, IRIN DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate Overclocking Conversion Rate Transient Response No Missing Codes No Missing Codes No Missing Codes (Note 2) VRIN = 2.5V VRIN = 2.5V IREF = 4mA V Applied = 2.5V
2.33 -
2.5 2 6
2.67 4 -
V mA V/oC
-
1.97 60
-
V mA V/oC
2.2 -
2.5 2.93 0.95
2.8 -
V k mA
1 -
95 1
80 -
MSPS MSPS MSPS Cycle
5
HI5630
Electrical Specifications
PARAMETER Over-Voltage Recovery Effective Number of Bits, ENOB Signal to Noise and Distortion Ratio, SINAD Signal to Noise Ratio, SNR Total Harmonic Distortion, THD Spurious Free Dynamic Range, SFDR Channel Crosstalk SAMPLING CLOCK INPUT Note 3 Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN CLOCK OUTPUT CL = 10pF (Note 3) Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Capacitance, CCOUT DIGITAL OUTPUTS CL = 10pF (Note 3) Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Capacitance, CDOUT TIMING CHARACTERISTICS Data Latency, tLAT Power-Up Initialization Sample Clock Pulse Width (Low) Sample Clock Pulse Width (High) Sample Clock Duty Cycle Variation POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVDD Digital Supply Voltage, DVDD Supply Current, ITOTAL Analog Current, IAVDD Digital5 Current, IDVDD Power Dissipation Standby Current Standby Power Offset Error PSRR, VOS Gain Error PSRR, FSE NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. AVDD or DVDD = 5V 5% AVDD or DVDD = 5V 5% 4.75 4.75 5.0 5.0 348 235 113 1.74 8 40 0.4 0.15 5.25 5.25 265 V V mA mA mA W mA mW LSB LSB Figure 9 For a Valid Sample Data Invalid Time 5 5 20 Cycles Cycles ns ns % IOH = 100A; DVDD = 5V IOL = 100A; DVDD = 5V 4.0 7 0.8 V V pF IOH = 100A IOL = 100A 4.0 7 0.8 V V pF Figure 10 Figure 10 VIH = 4.5V VIL = 0V -10.0 -10.0 4 0.4 7 +10.0 +10.0 V V A A pF AVDD = 5V, DVDD = 5V; Single Ended Inputs, VRIN = 2.5V; fS = 80MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Unless Otherwise Specified (Continued) TEST CONDITIONS 0.2V Overdrive fIN = 1MHz (Figure 11) fIN = 1MHz fIN = 1MHz (Figure 12) fIN = 1MHz fIN = 1MHz (Figure 13) MIN TYP 1 7.6 47.8 47.9 - 63 - 64 75 MAX UNITS Cycle Bits dB dB dB dB dB
6
HI5630 Timing Waveforms
ANALOG INPUT
CLOCK INPUT
SN - 1
HN - 1
SN
HN
SN + 1
HN + 1
SN + 2
SN + 5 HN + 5
S N + 6 HN + 6 S N + 7
HN + 7 S N + 8
HN + 8
INPUT S/H
1ST STAGE
B1 , N - 1
B1 , N
B1 , N + 1
B1 , N + 4
B1 , N + 5
B1 , N + 6
B1 , N + 7
2ND STAGE
B2 , N - 2
B2 , N - 1
B2 , N
B2 , N + 4
B2 , N + 5
B2 , N + 6
6TH STAGE
B9 , N - 5
B9 , N - 4
B9 , N
B9 , N + 1
B9 , N + 2
B9 , N + 3
DATA OUTPUT
DN - 4
DN - 3 tLAT
DN - 1
DN
DN + 1
DN + 2
NOTES: 4. SN : N-th sampling period. 5. HN : N-th holding period. 6. BM , N : M-th stage digital output corresponding to N-th sampled input. 7. DN : Final data output corresponding to N-th sampled input. FIGURE 1. HI5630 INTERNAL CIRCUIT TIMING
ANALOG INPUT tAP tAJ CLOCK INPUT 1.5V 1.5V tOD tH DATA OUTPUT 2.4V DATA N-1 DATA N 0.5V
FIGURE 2. HI5630 INPUT-TO OUTPUT TIMING
7
HI5630 Detailed Description
Theory of Operation
The HI5630 is a triple 8-Bit fully differential sampling pipeline A/D converter with digital error correction logic. Each of the three channels are identical so this discussion will only cover one channel. Figure 3 depicts the circuit for the front end differential-in-differential-out sample-and-hold (S/H). The switches are controlled by an internal sampling clock which is a non-overlapping two phase signal, 1 and 2 , derived from the master sampling clock. During the sampling phase, 1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of 1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, 2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The front end sample-and-hold output is a fully-differential, sampleddata representation of the analog input. The circuit not only performs the sample-and-hold function but will also convert a single-ended input to a fully-differential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 250MHz for the converter. which is controlled by the internal sampling clock. The function of the digital delay line is to time align the digital outputs of the identical two-bit subconverter stages with the corresponding output of the last stage flash converter before applying the results to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final ten bit digital data output of the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus on the 5th cycle of the clock after the analog sample is taken. This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital output data is synchronized to the external sampling clock by a double buffered latching technique. The digital output data is available in two's complement or offset binary format depending on the state of the Data Format Select (DFS) control input (see Table 1, A/D Code Table).
Internal Reference Voltage Output, VROUT
The HI5630 is equipped with an internal reference voltage generator, therefore, no external reference voltage is required. VROUT must be connected to VRIN when using the internal reference voltage. An internal band-gap reference voltage followed by an amplifier/buffer generates the precision +2.5V reference voltage used by the converter. A 8:1 array of substrate PNPs generates the "delta-VBE" and a two-stage op amp closes the loop to create an internal +1.25V band-gap reference voltage. This voltage is then amplified by a wide-band uncompensated operational amplifier connected in a gain-of-two configuration. An external, user-supplied, 1F capacitor connected from the VROUT output pin to analog ground is used to set the dominant pole and to maintain the stability of the operational amplifier.
1
VIN+
CH
1
VOUT+ VOUT-
1 2
CS -+ +-
VIN-
1
CS
1
CH
1
Reference Voltage Input, VRIN
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing diagram, identical pipeline subconverter stages, each containing a two-bit flash converter and a two-bit multiplying digital-to-analog converter, follow the S/H circuit with the last stage being a two bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. The output of each of the identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line
The HI5630 is designed to accept a +2.5V reference voltage source at the VREF IN input pin. Typical operation of the converter requires VRIN to be set at +2.5V. The HI5630 is tested with VRIN connected to VROUT yielding a fully differential analog input voltage range of 0.5V. The user does have the option of supplying an external +2.5V reference voltage. As a result of the high input impedance presented at the VRIN input pin, 3.0k typically, the external reference voltage being used is only required to source 1mA of reference input current. In the situation where an external reference voltage will be used an external 1F capacitor must be connected from the VROUT output pin to analog ground in order to maintain the stability of the internal operational amplifier. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, VRIN .
8
HI5630
DC Voltage Source, VDC
An internal band-gap reference voltage followed by an amplifier/buffer generates the precision +2.0V DC voltage source to the user to help simplify circuit design. The characteristics of the DC source is equivalent to the internal reference. coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal.
VIN+ VDC R C VIN+ HI5630 VDC VINVDC R VIN-
Analog Input, Differential Connection
The analog input to the HI5630 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figures 4 and 5) will deliver the best performance from the converter.
FIGURE 5. DC COUPLED DIFFERENTIAL INPUT
VIN+ R
VIN+ HI5630 VDC R
Analog Input, Single-Ended Connection
The configuration shown in Figure 6 may be used with a single ended AC coupled input.
VIN-
VIN-
VIN R VDC
VIN+ HI5630 VIN-
FIGURE 4. AC COUPLED DIFFERENTIAL INPUT
Since the HI5630 is powered by a single +5V analog supply, the analog input is limited to be between ground and +5V. For the differential input connection this implies the analog input common mode voltage can range from 0.25V to 4.75V. The performance of the ADC does not change significantly with the value of the analog input common mode voltage. A DC voltage source, VDC , equal to 2.0V (typical), is made available to the user to help simplify circuit design when using an AC coupled differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent DC bias source and stays well within the analog input common mode voltage range over temperature. For the AC coupled differential input (Figure 4) and with VRIN connected to VROUT , full scale is achieved when the VIN and VIN- input signals are 0.5VP- P , with -VIN being 180 degrees out of phase with VIN . The converter will be at positive full scale when the VIN+ input is at VDC + 0.25V and the VIN- input is at VDC - 0.25V (VIN+ - VIN- = +0.5V). Conversely, the converter will be at negative full scale when the VIN+ input is equal to VDC - 0.25V and VIN- is equal to VDC + 0.25V (VIN+ - VIN- = -0.5V). The analog input can be DC coupled (Figure 5) as long as the inputs are within the analog input common mode voltage range (0.25V VDC 4.75V). The resistors, R, in Figure 5 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC
FIGURE 6. AC COUPLED SINGLE ENDED INPUT
Again, with VRIN connected to VROUT , if VIN is a 1VP-P sinewave, then VIN+ is a 1.0VP-P sinewave riding on a positive voltage equal to VDC . The converter will be at positive full scale when VIN+ is at VDC + 0.5V (VIN+ - VIN- = +0.5V) and will be at negative full scale when VIN+ is equal to VDC - 0.5V (VIN+ - VIN- = -0.5V). Sufficient headroom must be provided such that the input voltage never goes above +5V or below AGND. In this case, VDC could range between 0.5V and 4.5V without a significant change in ADC performance. The simplest way to produce VDC is to use the DC bias source, VDC , output of the HI5630. The single ended analog input can be DC coupled (Figure 1) as long as the input is within the analog input common mode voltage range. The resistor, R, in Figure 7 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source may give better overall system performance if it is first converted to differential before driving the HI5630.
9
HI5630
VIN VDC R C VDC HI5630 VIN+
VIN-
path. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5630 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply should be isolated with a ferrite bead from the digital supply. Refer to the application note "Using Intersil High Speed A/D Converters" (AN9214) for additional considerations when using high speed converters.
FIGURE 7. DC COUPLED SINGLE ENDED INPUT
Digital Output Control and Clock Requirements
The HI5630 provides a standard high-speed interface to external TTL logic families. In order to ensure rated performance of the HI5630, the duty cycle of the clock should be held at 50% 5%. It must also have low jitter and operate at standard TTL levels. Performance of the HI5630 will only be guaranteed at conversion rates above 1MSPS. This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1MSPS will have to be performed before valid data is available. A Data Format Select (DFS) pin is provided which will determine the format of the digital data outputs. When at logic low, the data will be output in offset binary format. When at logic high, the data will be output in two's complement format. Refer to Table 1 for further information.
Static Performance Definitions
Offset Error (VOS) - The midscale code transition should occur at a level 1/4 LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point. Full-Scale Error (FSE) - The last code transition should occur for an analog input that is 3/4 LSB below Positive Full Scale (+FS) with the offset error removed. Full scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) - DNL is the worst case deviation of a code width from the ideal value of 1 LSB. Integral Linearity Error (INL) - INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Power Supply Sensitivity - Each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error (in LSBs) is noted.
Supply and Ground Considerations
The HI5630 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal
TABLE 1. A/D CODE TABLE OFFSET BINARY OUTPUT CODE (DFS LOW) M S B D7 1 1 1 0 0 0 D6 1 1 0 1 0 0 D5 1 1 0 1 0 0 D4 1 1 0 1 0 0 D3 1 1 0 1 0 0 D2 1 1 0 1 0 0 D1 1 1 0 1 0 0 L S B D0 1 1 0 1 0 0 TWO'S COMPLEMENT OUTPUT CODE (DFS HIGH) M S B D7 0 0 0 1 1 1 D6 1 1 0 1 0 0 D5 1 1 0 1 0 0 D4 1 1 0 1 0 0 D3 1 1 0 1 0 0 D2 1 1 0 1 0 0 D1 1 1 0 1 0 0 L S B D0 1 1 0 1 0 0
CODE CENTER DESCRIPTION +Full Scale (+FS) - 7/16 LSB +FS 1 7/
16 LSB
DIFFERENTIAL INPUT VOLTAGE (VIN+ - VIN-) 0.498291V 0.494385V 2.19727mV -1.70898V -0.493896V -0.497803V
+ 9/16 LSB - 7/16 LSB -FS + 19/16 LSB -Full Scale (-FS) + 9/16 LSB NOTE:
8. The voltages listed above represent the ideal center of each output code shown with VRIN = +2.5V.
10
HI5630 Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5630. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is typically -0.5dB down from full scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. The Effective Number of Bits (ENOB) is calculated from the SINAD data by: ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5dB (Typical). VCORR adjusts the SINAD, and hence the ENOB, for the amount the analog input signal is backed off from full scale. Signal To Noise and Distortion Ratio (SINAD) - SINAD is the ratio of the measured RMS signal to RMS sum of all the other spectral components below the Nyquist frequency, fS/2, excluding DC. Signal To Noise Ratio (SNR) - SNR is the ratio of the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components below fS /2 excluding the fundamental, the first five harmonics and DC. Total Harmonic Distortion (THD) - THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal. 2nd and 3rd Harmonic Distortion - This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal. Spurious Free Dynamic Range (SFDR) - SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spectral component in the spectrum below fS /2. Intermodulation Distortion (IMD) - Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present at the inputs. The ratio of the measured signal to the distortion terms is calculated. The terms included in the calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2), (f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB below full scale. Transient Response - Transient response is measured by providing a full-scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 8-bit accuracy. Over-Voltage Recovery - Over-Voltage Recovery is measured by providing a full-scale transition to the analog input of the ADC which overdrives the input by 200mV, and 11 measuring the number of cycles it takes for the output code to settle within 8-bit accuracy. Full Power Input Bandwidth (FPBW) - Full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has an amplitude which swings from -FS to +FS. The bandwidth given is measured at the specified sampling frequency.
Video Definitions
Differential Gain and Differential Phase are two commonly found video specifications for characterizing the distortion of a chrominance signal as it is offset through the input voltage range of an ADC. Differential Gain (DG) - Differential Gain is the peak difference in chrominance amplitude (in percent) relative to the reference burst. Differential Phase (DP) - Differential Phase is the peak difference in chrominance phase (in degrees) relative to the reference burst.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions. Aperture Delay (tAP) - Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter (tAJ) - Aperture jitter is the RMS variation in the aperture delay due to variation of internal clock path delays. Data Hold Time (tH) - Data hold time is the time to where the previous data (N - 1) is no longer valid. Data Output Delay Time (tOD) - Data output delay time is the time from the rising edge of the external sample clock to where the new data (N) is valid. Data Latency (tLAT) - After the analog sample is taken, the digital data representing an analog input sample is output to the digital data bus on the 7th cycle of the clock after the analog sample is taken. This is due to the pipeline nature of the converter where the analog sample has to ripple through the internal subconverter stages. This delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital data lags the analog input sample by 7 sample clock cycles. Power-Up Initialization - This time is defined as the maximum number of clock cycles that are required to initialize the converter at power-up. The requirement arises from the need to initialize the dynamic circuits within the converter.
HI5630 Typical Performance Curves
7.7 7.6 4.5 7.5 7.4 ENOB (BITS) VIH (V) 7.3 7.2 7.1 7.0 6.9 6.8 6.7 0 10 20 30 40 50 CLOCK FREQUENCY (MHz) 2.0 30 35 40 45 50 55 DUTY CYCLE (%) 60 65 70 3.0 2.5 4.0 3.5 PASSING RANGE 5.0
FIGURE 8. ENOB vs INPUT FREQUENCY (fCLK = 80MHz)
FIGURE 9. DUTY CYCLE vs VIH
5.0 4.5 PASSING RANGE ENOB (BITS) 4.0 VIH (V) 3.5 3.0 2.5 2.0 0 200m 400m 600m 800m VIL (V) 1.00 1.20 1.40 1.6
7.70 7.65 7.60 7.55 7.50 7.45 7.40 7.35 7.30 7.25 7.20 0
BLUE GREEN
RED
25 70 TEMPERATURE (oC)
85
FIGURE 10. VIH vs VIL
FIGURE 11. ENOB vs TEMPERATURE
47.5 BLUE 47.0 46.5 SNR (dB) 46.0 45.5 45.0 44.5 0 25 70 TEMPERATURE (oC) 85 GREEN
68 66
BLUE
RED RED SFDR (dB) 64 62 60 58 56 0 25 70 TEMPERATURE (oC) 85
GREEN
FIGURE 12. SNR vs TEMPERATURE
FIGURE 13. SFDR vs TEMPERATURE
12
HI5630 Typical Performance Curves
0.7 RED 0.6 0.5 1.964 INL (LSB) VDC (V) 0.4 0.3 0.2 0.1 0 0 25 70 TEMPERATURE (oC) 85 GREEN BLUE 1.962 RED VDC 1.960 1.958 1.956 1.954 1.952 0 25 70 TEMPERATURE (oC) 85 BLUE VDC GREEN VDC
(Continued)
1.970 1.968 1.966
FIGURE 14. INL vs TEMPERATURE
FIGURE 15. VDC vs TEMPERATURE
2.476 2.474 VREF (V) WITH 4mA LOAD 2.472 2.470 2.468 2.466 2.464 2.462 0 25 70 TEMPERATURE (oC) 85 VREF (4mA LOAD) CURRENT (mA)
300 I TOTAL 250 200 150 100 50 0 0 25 70 TEMPERATURE (oC) 85 I AVDD
I DVDD
FIGURE 16. VREF vs TEMPERATURE
FIGURE 17. SUPPLY CURRENT (mA) vs TEMPERATURE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13

▲Up To Search▲

Price & Availability of HI56308CN

	To Download HI56308CN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .